Design functionality can be
verified early in the design process. Design simulation at this higher level,
before implementation at the gate level, allows you to evaluate architectural
and design decisions. Coupling HDL Compiler with logic synthesis tools, you can
automatically convert an HDL description to a gate-level implementation in a
target technology.HDL descriptions provide technology independent documentation
of a design and its functionality. Since the initial HDL design description is
technology-independent, you can use it again to generate the design in a
different technology, without having to translate from the original technology.
Saturday, 5 May 2012
Properties of HDL
Can represent design at different
levels of abstraction.
Technology independent.
Functional verification of the
design can be done
Parameterization-enables modules
properties, e.g. bus width to be defined at synthesis time.
Design at high level of
abstraction enables technology mapping.
Maximizes design re-use.
Verilog
The complexity of
hardware design has grown exponentially in the last decade. The exponential
growth is fueled by new advances in design technology as well as the advances
in fabrication technology . The usage of hardware description language to
model, simulate, synthesize, analyze, and test the design has been a corner
stone of this rapid development. Verilog
is the first hardware description language that was designed to be the language
of choice in this domain. It is designed to enable descriptions of complex and
large designs in a precise and succinct manner. It can facilitate descriptions
of advances in architectures of design such as pipelining, cache management,
and branch predictions. A smooth top-down design flow is possible with verilog
based designs. It is also designed to facilitate new ECAD technolo gies such as synthesis and formal
verification and simulation. It was designed to unify design process (including
behavioral, rtl, gates, stimulus, switches, user-interface, test benches, and
unified interactive and batch modes). It is designed to leverage advances in
software development for hardware design.
A hardware description language describes hardware using a language. For every piece of hardware there exists a corresponding language (and viceversa). The correspondence is explained below in terms of building blocks in hardware and the constructs in the language. The building blocks in hardware design is dependent on the methodology being used. A design process consists of top-down and bottom up and a mixture of these two styles. Verilog is a powerful tool in the top-down design methodology and is capable of supporting the bottom up style and consequently the mixed approach as well.
Verilog defines a set of words to have special meaning. These words are reserved and cannot be used as identifiers or labels in a verilog model. The type of a statement is identified by the first word in the statement that is keyword. Examples of these will be ‘always’, ‘and’, ‘assign’, etc. when a statement begins with the word always, there is a special meaning of an always loop attached to that statement. The set of keywords defines the scope or the contents of the language. In other words, the set of features in verilog can be characterized by the set of keywords as defined below.
A module is the principle design entity in verilog. The first line of a module declaration specifies the name and port list (arguments). The next few lines specify the i/o type (input, output or inout) and width of each port. The default port width is 1 bit. Then the port variables must be declared wire, wand, reg. The default is wire. Typically inputs are wire since their data is latched outside the module. Outputs are type reg if their signals were stored inside an always or initial block.
Syntax:
Module module_name (port_list);
Input [msb:lsb]
input_port_list;
Output [msb:lsb]
output_port_list;
Inout [msb:lsb]
inout_port_list;
Statements…….
Endmodule
Hardware description language
Imagine design engineers needing
to hand draw millions of transistors in their schematic. The task was simply
impossible. A more efficient and productive method was needed to allow
designers to create schematics with large numbers of logic gates within a reasonable
timeframe. This lead to the development
of Hardware Description language (HDL). This new method allows a designer to
code the logic functionality of a circuit in HDL. The code is then synthesized
into logic gates using a synthesis tool.
The industry provides two languages for
hardware description
1.
VHSIC
Hardware description language
2.
Verilog Hardware description language
Literature survey
A
gate that implements any bijective function involving n inputs and n outputs is
called an n*n reversible logic gate. There exist many reversible gates in the
literature. Among them 2*2 Feynman gate,3*3 Fredkin gate,3*3 Tofolli gate,3*3
Peres gate are the most referred [5,10]. Feynman (FG), Fredkin (FRG) and Peres
(PG) gates are one through gates, that is, one of its output lines is identical
to one of its input lines. On the other hand, Tofolli gate is two through, that
is, two of its outputs are identical to two of its inputs. It can be easily
verified that all of these gates are reversible. Each gate has an equal number
of input and output lines. For each input combination there is a unique output
combination.
Introduction
Reversible circuits are those circuits that do
not lose information and reversible computation in a system can be performed
only when the system comprises of reversible gates. These circuits can generate
unique output vector from each input vector, and vice versa, that is, there is
a one-to-one mapping between the input and output vectors. In reversible logic circuit
the number of inputs must be equal to the number of outputs. For each input
pattern there must be a unique output pattern. For each output will be used
only once, (that is) no fan out is allowed. The resulting circuit
must be acyclic.
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