Verilog

The complexity of hardware design has grown exponentially in the last decade. The exponential growth is fueled by new advances in design technology as well as the advances in fabrication technology . The usage of hardware description language to model, simulate, synthesize, analyze, and test the design has been a corner stone of this rapid development.  Verilog is the first hardware description language that was designed to be the language of choice in this domain. It is designed to enable descriptions of complex and large designs in a precise and succinct manner. It can facilitate descriptions of advances in architectures of design such as pipelining, cache management, and branch predictions. A smooth top-down design flow is possible with verilog based designs. It is also designed to facilitate new ECAD technolo  gies such as synthesis and formal verification and simulation. It was designed to unify design process (including behavioral, rtl, gates, stimulus, switches, user-interface, test benches, and unified interactive and batch modes). It is designed to leverage advances in software development for hardware design.

             
 A hardware description language describes hardware using a language. For every piece of hardware there exists a corresponding language (and viceversa). The correspondence is explained below in terms of building blocks in hardware and the constructs in the language. The building blocks in hardware design is dependent on the methodology being used. A design process consists of top-down and bottom up and a mixture of these two styles. Verilog is a powerful tool in the top-down design methodology and is capable of supporting the bottom up style and consequently the mixed approach as well.

             
Verilog defines a set of words to have special meaning. These words are reserved and cannot be used as identifiers or labels in a verilog model. The type of a statement is identified by the first word in the statement that is keyword. Examples of these will be ‘always’, ‘and’, ‘assign’, etc. when a statement begins with the word always, there is a special meaning of an always loop attached to that statement. The set of keywords defines the scope or the contents of the language. In other words, the set of features in verilog can be characterized by the set of keywords as defined below.

           
A module is the principle design entity in verilog. The first line of a module declaration specifies the name and port list (arguments). The next few lines specify the i/o type (input, output or inout) and width of each port. The default port width is 1 bit. Then the port variables must be declared wire, wand, reg. The default is wire. Typically inputs are wire since their data is latched outside the module. Outputs are type  reg  if their signals were stored inside an always or initial block.  

Syntax:

Module  module_name (port_list);

Input [msb:lsb] input_port_list;

Output [msb:lsb] output_port_list;

Inout [msb:lsb] inout_port_list;

Statements…….

Endmodule