Verilog
is a free-format language like c-language.
2.
White space can be used freely
3.
Verilog is a case-sensitive language.
4.
User provided names for the verilog objects in the descriptions.
5.
Legal characters are “a-z”, “A-Z”, “0-9”,
“_”, and “$”.
6.
First character has to be a letter or an “_”.
7.
Example: Count, _R2D2, Fives$
8.
Predefined identifiers to define the language constructs.
9.
All keywords are defined in the lower case cannot be used as identifiers.
10. Example: initial, assign, module
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