Tasks
are like procedures in other programming
languages, e. g., may have zero or more arguments and do not return a value.
Functions act like function subprograms in other languages. Except A
Verilog function must execute during one simulation time unit. That is, no time
controlling statements, i. e., no delay control (#), event control (@)
or wait statements, allowed. A task may contain controlled statements. A
Verilog function cannot invoke
(call, enable) a task; whereas task may call other tasks and functions.
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