Verilog digital logic simulator tools allow you to perform the following tasks in the design process without building a hardware prototype:

1. Determine the feasibility of new design ideas
2. Try more than one approach to a design problem
3. Verify functionality
4. Identify design problems.

Overview Of Reversible Logic Synthesis Methods

1.  Composition methods:
The idea is to compose a reversible block using small and well known reversible gates. The reversible block should be easy to use. Then, a modification of a conventional logic synthesis procedure is applied to synthesize a network. The resulting network will be reversible as a network essentially consisting of reversible gates.

2.  Decomposition methods:
 Decomposition methods can be characterized as a top down reduction of the function from its outputs to its inputs. During the design procedure a function is supposed to be decomposed into a combination of several specific functions each of which is realized as a separate reversible network .An example of a decomposition method can be found in where synthesis appears to be a reduction of the output to the form of the input. The decomposition and composition methods can be multilevel. Observe that the composition and decomposition methods form a very general and powerful tool of logic synthesis. In fact, most of the algorithms can be classified as either composition or decomposition. Using Lemma 1, one can notice the duality of the composition and decomposition methods; a composition design procedure for a reversible function f is a decomposition procedure for fi1.

Advantages of storing the Intermediate results

The achievements obtained using this method is:

1. No erasing of bits is done as in the irreversible process.
2. Heat dissipation is not there as the bits are not erased and hence power is saved.
3. And the inputs can be obtained from the outputs.

      

Main reasons of Important role of HDL in mordern design methodology

Design functionality can be verified early in the design process. Design simulation at this higher level, before implementation at the gate level, allows you to evaluate architectural and design decisions. Coupling HDL Compiler with logic synthesis tools, you can automatically convert an HDL description to a gate-level implementation in a target technology.HDL descriptions provide technology independent documentation of a design and its functionality. Since the initial HDL design description is technology-independent, you can use it again to generate the design in a different technology, without having to translate from the original technology.

Procedure vs Continuos assignment statement

Procedural assignment changes the state of a register

  sequential logic

  Clock controlled

Continuous statement is used to model combinational logic. Continuous assignments drive wire variables and are evaluated and updated whenever an input operand changes value. It is important to understand and remember the difference.

Tasks and Functions

Tasks are like procedures in other programming languages, e. g., may have zero or more arguments and do not return a value. Functions act like function subprograms in other languages. Except A Verilog function must execute during one simulation time unit. That is, no time controlling statements, i. e., no delay control (#), event control (@) or wait statements, allowed. A task may contain controlled statements. A Verilog function cannot invoke (call, enable) a task; whereas task may call other tasks and functions.

Lexical convections

Verilog is a free-format language like c-language.

2. White space can be used freely

3. Verilog is a case-sensitive language.

4. User provided names for the verilog objects in the descriptions.

5. Legal characters are “a-z”, “A-Z”, “0-9”,   “_”, and “$”.

6. First character has to be a letter or an “_”.

7. Example: Count,  _R2D2, Fives$

8. Predefined identifiers to define the language constructs.

9. All keywords are defined in the lower case cannot be used as identifiers.

10. Example: initial, assign, module