Why Verilog?

The complexity of hardware design has grown exponentially in the last decade. The exponential growth is fueled by new advances in design technology as well as the advances in fabrication technology . The usage of hardware description language to model, simulate, synthesize, analyze, and test the design has been a corner stone of this rapid development.  Verilog is the first hardware description language that was designed to be the language of choice in this domain. It is designed to enable descriptions of complex and large designs in a precise and succinct manner. It can facilitate descriptions of advances in architectures of design such as pipelining, cache management, and branch predictions. A smooth top-down design flow is possible with verilog based designs. It is also designed to facilitate new ECAD technologies such as synthesis and formal verification and simulation. It was designed to unify design process (including behavioral, rtl, gates, stimulus, switches, user-interface, test benches, and unified interactive and batch modes). It is designed to leverage advances in software development for hardware design.
            
A hardware description language describes hardware using a language. For every piece of hardware there exists a corresponding language (and viceversa). The correspondence is explained below in terms of building blocks in hardware and the constructs in the language. The building blocks in hardware design is dependent on the methodology being used. A design process consists of top-down and bottom up and a mixture of these two styles. Verilog is a powerful tool in the top-down design methodology and is capable of supporting the bottom up style and consequently the mixed approach as well.
           

Verilog defines a set of words to have special meaning. These words are reserved and cannot be used as identifiers or labels in a verilog model. The type of a statement is identified by the first word in the statement that is keyword. Examples of these will be ‘always’, ‘and’, ‘assign’, etc. when a statement begins with the word always, there is a special meaning of an always loop attached to that statement. The set of keywords defines the scope or the contents of the language. In other words, the set of features in verilog can be characterized by the set of keywords as defined below.
          

A module is the principle design entity in verilog. The first line of a module declaration specifies the name and port list (arguments). The next few lines specify the i/o type (input, output or inout) and width of each port. The default port width is 1 bit. Then the port variables must be declared wire, wand, reg. The default is wire. Typically inputs are wire since their data is latched outside the module. Outputs are type  reg  if their signals were stored inside an always or initial block






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Capabilities of Verilog

 
The following are the major capabilities that the language provides along with the features that differentiate it from other hardware description languages.


The language can be used as an exchange medium between chip vendors and CAD tool users. Different chip vendors can provide Verilog descriptions of their components to system designers. CAD tool users can use it to capture the behavior of the design at a high level of abstraction for functional simulation. The  language can also be used as a communication medium between different CAD and CAE tools. For example, a schematic capture program may be used to generate a Verilog description for the design, which can be used as an input to a simulation program. The language supports hierarchy; that is, a digital system can be modeled as a set of interconnected components; each component, in turn, can be modeled as a set of interconnected
components. The language supports flexible design methodologies: top-down, bottom-up, or mixed.

The language is not technology-specific, but is capable of supporting technology specific features. It can also support various hardware technologies; for example, we may define new logic typed and new components; we may also specify technology-specific attributes. By being technology-independent, the same model can be synthesized into different vendor libraries. It supports both synchronous and asynchronous timing models. Various digital modeling techniques, such as finite-state machine descriptions, Algorithmic descriptions, and Boolean equations, can be modeled using the language. The language is publicity available, human-readable, all, it and, above is not proprietary. It is an IEEE and ANSI standard; therefore, models described using this  language are portable. The language supports three basic different description styles: dataflow, structural, and behavioral. A design may also be expressed in any combination of these three descriptive styles. It supports wide range of abstraction levels ranging from abstract behavioral descriptions to vary precise gate-level descriptions. It does not, however, support modeling at or below the transistor level. It allows a design to be captured at a mixed level using a single coherent language. Arbitrarily large designs can be modeled using the language, and there are no limitations on the size of a design. The language has elements that make large-scale designs modeling easier; for example, components, functions, procedure, and packages. Test benches can be written using the same language to test other Verilog models. A model can not only describe the functionality of a design, but can also contain information about the design itself in terms of user-defined attributes, such as total area and speed. A common language can be used to describe library components from different vendors. Tools that understand Verilog  models will have no difficulty in reading models from a variety of vendors since the language is a standard. Behavioral models that conform to a certain synthesis descriptions style are capable of being synthesized to gate-level descriptions. The capability of defining new data types provides the power to describe and simulate a new design technique at a very high level of abstraction without any concern about the implementation details

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Overview of Reversible Logic Synthesis Methods.

Such a variety of different reversible gates results in a variety of different approaches to reversible logic synthesis. Fortunately, the basic analysis of different techniques of reversible logic synthesis was successfully done in one of Perkowski's work. Here, we use and expand this approach to the classification of reversible synthesis methods.

Composition methods: The idea is to compose a reversible block using small and well known reversible gates. The reversible block should be easy to use. Then, a modification of a conventional logic synthesis procedure is applied to synthesize a network. The resulting network will be reversible as a network essentially consisting of reversible gates.

 Decomposition methods: Decomposition methods can be characterized as a top down reduction of the function from its outputs to its inputs. During the design procedure a function is supposed to be decomposed into a combination of several specific functions each of which is realized as a separate reversible network .An example of a decomposition method can be found in where synthesis appears to be a reduction of the output to the form of the input. The decomposition and composition methods can be multilevel. Observe that the composition and decomposition methods form a very general and powerful tool of logic synthesis. In fact, most of the algorithms can be classified as either composition or decomposition. Using Lemma 1, one can notice the duality of the composition and decomposition methods; a composition design procedure for a reversible function f is a decomposition procedure for f¡1.

 Factorization methods: Factorization is another powerful logic design tool. Its idea is in choosing a Boolean operation, for instance, ? (often multiplication or EXOR) for a function f and ¯ending two functions f1 and f2 such that:
 f = f1? f2;
 for the synthesis cost metrics the cost of f is smaller than the sum of costs of f1 and f2 plus a weight associated with the Operation. In general, the Operation does not have to be a binary operation, but may be an arbitrary multiple output function of several arguments. To our knowledge, the factorization tool was first applied to reversible logic design in.






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Injective Function

In mathematics, an injective function is a function that preserves distinctness: it never maps distinct elements of its domain to the same element of its codomain. In other words, every element of the function's codomain is mapped to by at most one element of its domain. If in addition all of the elements in the codomain are in fact mapped to by some element of the domain, then the function is said to be bijective. Read more

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The Reversibility of Physics and Reversible Computing

Landauer's principle (and indeed, the second law of thermodynamics itself) can also be understood to be a direct logical consequence of the underlying reversibility of physics, as is reflected in the general Hamiltonian formulation of mechanics, and in the unitary time-evolution operator of quantum mechanics more specifically.In the context of reversible physics, the phenomenon of entropy increase (and the observed arrow of time) can be understood to be consequences of the fact that our evolved predictive capabilities are rather limited, and cannot keep perfect track of the exact reversible evolution of complex physical systems, especially since these systems are never perfectly isolated from an unknown external environment, and even the laws of physics themselves are still not known with complete precision. Thus, we (and physical observers generally) always accumulate some uncertainty about the state of physical systems, even if the system's true underlying dynamics is a perfectly reversible one that is subject to no entropy increase if viewed from a hypothetical omniscient perspective in which the dynamical laws are precisely known. Read more

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Universality and Toffoli gate

Any reversible gate must have the same number of input and output bits, by the pigeonhole principle. For one input bit, there are two possible reversible gates. One of them is NOT. The other is the identity gate which maps its input to the output unchanged. For two input bits, the only non-trivial gate is the controlled NOT gate which XORs the first bit to the second bit and leaves the first bit unchanged. Read more

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Quantum gate

In quantum computing and specifically the quantum circuit model of computation, a quantum gate (or quantum logic gate) is a basic quantum circuit operating on a small number of qubits. They are the building blocks of quantum circuits, like classical logic gates are for conventional digital circuits. Continue Reading







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